1. Field of the Invention
This invention is related to the field of integrated circuit testing.
2. Description of the Related Art
Integrated circuits generally must be tested to detect whether or not the circuits were fabricated correctly. The testing generally includes functional testing, which may be performed at low speeds and may detect circuitry that is not working at all (e.g. due to open connections or shorts in the interconnect, devices that were not fabricated properly, etc.). The testing also includes at-speed testing to determine if the circuitry will operating properly at various operating points (e.g. selected operating frequencies for the clocks provided to the integrated circuit and/or generated within the integrated circuit, selected operating voltages for those frequencies, etc.).
Traditionally, integrated circuit testing is performed using automated test equipment (ATE). An ATE can connect to the integrated circuit and test it using test vectors supplied by the integrated circuit designers, micro-architects, design verification engineers, design for test (DFT) engineers and silicon validation engineers. Each test vector can specify values to be driven by the ATE on inputs of the integrated circuit and values expected by the ATE on outputs of the integrated circuit for a given period of time. The period of time can be a clock cycle of a clock supplied to the integrated circuit, one half of the clock cycle, or any other period of time (e.g. a period specified in nanoseconds or picoseconds). The ATE can drive the inputs as specified in the test vector and sense the outputs for comparison to the test vector, or for comparison to an expected different output pattern. If the integrated circuit passes all the test vectors, the integrated circuit can be viewed as fabricated correctly and sellable. If the integrated circuit fails one or more test vectors, it can be binned, or removed from the sales channel and scrapped (or sold at a lower operating frequency, if it fails at-speed tests).
As integrated circuits grow in complexity, the testing of the integrated circuits can also become more complex. Increased complexity can be experienced, for example, if the integrated circuit includes one or more “clock domains” that can be operating at different frequencies concurrently. In such cases, some of the interfaces within the integrated circuit that cross clock domains are asynchronous. The timing of communications over the asynchronous interfaces can be unpredictable (within a window of a few clock cycles). Since traditional test vectors specify expected outputs over a certain period of time, the unpredictability of the timing (which is correct operation and should not be detected as a failure) is made more difficult. In some cases, the unpredictability can make traditional testing using test vectors practically impossible. The number of combinations of correct inputs and outputs can be very large. Additionally, the timing of some inputs can change based on the timing at which outputs are detected, which would require the ATE to change the inputs on the fly, during testing.
Complex integrated circuits such as systems on a chip (SOCs) can also complicate testing. SOCs include a variety of different functional blocks or components, such as processors, peripherals, on chip memory and caches, etc. Testing the blocks in a reasonable amount of test time can be challenging.